Stacked memory with redundancy
US-2015357002-A1 · Dec 10, 2015 · US
US8995212B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8995212-B2 |
| Application number | US-201213585169-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 14, 2012 |
| Priority date | May 25, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A column repair circuit of a semiconductor memory apparatus includes a plurality of mats and performs a column repair operation to replace failed cells among a plurality of memory cells provided in the mats. The column repair circuit includes two or more fuse units configured to perform the column repair operation. Each of the fuse units includes a plurality of fuses, and is configured in such a manner that m mats correspond to one fuse or n mats correspond to one fuse, where m and n are natural numbers equal to or more than 1 and different from each other.
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What is claimed is: 1. A column repair circuit of a semiconductor memory apparatus, which includes a plurality of mats and performs a column repair operation to replace failed cells among a plurality of memory cells provided in the mats, the column repair circuit comprising: two or more fuse units configured to perform the column repair operation; and a combined mat address generation unit configured to receive mat addresses and generate first combined mat addresses combined in…
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