Stacked memory with redundancy
US-2015357002-A1 · Dec 10, 2015 · US
Circuits, apparatuses, and methods for address scrambling
US9104588B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104588-B2 |
| Application number | US-201313783035-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 1, 2013 |
| Priority date | Mar 1, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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Abstract
Official abstract text for this publication.
Circuits, apparatuses, and methods are disclosed for address scrambling in integrated circuits. One example apparatus includes a plurality of data regions, each of the plurality of data regions configured to provide a respective portion of data responsive to a physical address provided by a respective decode circuit. The plurality of data regions are configured to provide their respective portions of data responsive to a common logical address. The common logical address is scrambled such that a plurality of different physical addresses are provided to the plurality of data regions.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus, comprising: a plurality of data regions, each of the plurality of data regions configured to provide a respective portion of data responsive to a physical address provided by a respective decode circuit, the plurality of data regions configured to provide respective portions of data responsive to a common logical address; wherein the common logical address is scrambled such that a plurality of different physical addresses are provided to the…
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- G11C29/808Primary
Physics · mapped topic
Physics · mapped topic
- G06F11/10Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US9104588B2 cover?
- Circuits, apparatuses, and methods are disclosed for address scrambling in integrated circuits. One example apparatus includes a plurality of data regions, each of the plurality of data regions configured to provide a respective portion of data responsive to a physical address provided by a respective decode circuit. The plurality of data regions are configured to provide their respective porti…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C29/808. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).