Mos capacitors for variable capacitor arrays and methods of forming the same
US-2016294366-A1 · Oct 6, 2016 · US
Integrated circuits and methods for monitoring forward and reverse back biasing
US8994446B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994446-B2 |
| Application number | US-201313930657-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 28, 2013 |
| Priority date | Jun 28, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.
First claim
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What is claimed is: 1. An integrated circuit, comprising: a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provide…
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- What does patent US8994446B2 cover?
- An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage rang…
- Who is the assignee on this patent?
- Pietri Stefano, Dao Chris C, Jarrar Anis M, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G05F3/205. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).