Method for forming source/drain contacts
US-2024379814-A1 · Nov 14, 2024 · US
MOS devices having non-uniform stressor doping
US8994097B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994097-B2 |
| Application number | US-201213415611-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 8, 2012 |
| Priority date | Mar 8, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations.
First claim
Opening claim text (preview).
What is claimed is: 1. A device comprising: a semiconductor substrate; a gate stack over the semiconductor substrate; a gate spacer on an edge of the gate stack; and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor region comprises: a first stressor region having a first p-type impurity concentration; a second stressor region over the first stressor region, wherein the second stressor region ha…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8994097B2 cover?
- A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has…
- Who is the assignee on this patent?
- Lin Mei-Hsuan, Lin Chih-Hsun, Chu Ching-Hua, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10D62/021. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).