Reduced resistance SiGe FinFET devices and method of forming same

Patent metadata

Field	Value
Publication number	US-8994072-B2
Application number	US-201314022917-A
Country	US
Kind code	B2
Filing date	Sep 10, 2013
Priority date	Jun 6, 2013
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins.

First claim

We claim;

1. A fin field-effect transistor (FinFET) device, comprising:
a substrate;
a gate structure formed on the substrate, the gate structure comprising:
a gate dielectric and gate metal; and
a silicon germanium (SiGe) fin formed under the gate dielectric and the gate metal; and

a source drain region adjacent the gate structure, wherein the source drain region comprises:
a merged epitaxial region including a dopant; and
a silicon fin; and

a junction between the…

Assignees

• IBM

Inventors

• Kerber Pranita
• Ouyang Qiping C
• Reznicek Alexander

Classifications

• H10D30/62 Primary

  Electricity · mapped topic

• H10D30/024 Primary

  Electricity · mapped topic

• H10D62/822

  Electricity · mapped topic

• H10D64/017

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic