Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integration

US8994048B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994048-B2
Application numberUS-96411710-A
CountryUS
Kind codeB2
Filing dateDec 9, 2010
Priority dateDec 9, 2010
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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A semiconductor device has a substrate with a first and second recess formed in a surface of the substrate using a wet etch process. The second recess can have a size different from a size of the first recess. A plurality of conductive vias are formed in a surface of the first and second recesses using a dry etch process. A first conductive layer is formed over the surface of the substrate, over curved side walls of the first and second recesses, and electrically connected to the plurality of conductive vias. A first and second semiconductor die are mounted into the first and second recesses respectively. The second semiconductor die can have a size different from a size of the first semiconductor die. The first and second semiconductor die are electrically connected to the first conductive layer. An interconnect structure is electrically connected to the plurality of conductive vias.

First claim

Opening claim text (preview).

What is claimed: 1. A method of making a semiconductor device, comprising: providing a substrate; forming a first recess in a surface of the substrate; forming a plurality of conductive vias in a surface of the first recess; forming a first conductive layer over the surface of the substrate over a curved side wall of the first recess and electrically connected to the plurality of conductive vias; disposing a first semiconductor die within the first recess electrically conn…

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What does patent US8994048B2 cover?
A semiconductor device has a substrate with a first and second recess formed in a surface of the substrate using a wet etch process. The second recess can have a size different from a size of the first recess. A plurality of conductive vias are formed in a surface of the first and second recesses using a dry etch process. A first conductive layer is formed over the surface of the substrate, ove…
Who is the assignee on this patent?
Choi Joonyoung, Kang Yonghee, Stats Chippac Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).