Systems and methods of testing memory devices
US-2024387303-A1 · Nov 21, 2024 · US
US8994022B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994022-B2 |
| Application number | US-201213443778-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 10, 2012 |
| Priority date | Apr 11, 2011 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.
Opening claim text (preview).
The invention claimed is: 1. A method of evaluating a semiconductor wafer dicing process, the method comprising: providing evaluation lines extending from an evaluation circuit into a first street of a plurality of streets on a wafer, the wafer further including functional circuits, the evaluation circuit and the functional circuits being arranged in columns and rows that are separated by the plurality of streets, the evaluation lines extending from a perimeter of the evaluation c…
Electricity · mapped topic
Electricity · mapped topic
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