Metal gate stack structure and manufacturing method
US-9525046-B2 · Dec 20, 2016 · US
Method of patterning a metal gate of semiconductor device
US8993452B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993452-B2 |
| Application number | US-201313745446-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 18, 2013 |
| Priority date | Aug 22, 2008 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.
First claim
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What is claimed is: 1. A method of fabricating a gate structure, comprising: forming a gate dielectric layer on a semiconductor substrate, wherein the gate dielectric includes a first high-k dielectric; forming a metal layer on the gate dielectric layer; forming a hard mask layer on the metal layer, wherein the hard mask layer includes a second high-k dielectric; patterning the hard mask layer and the metal layer, wherein the patterning defines a first portion and a second p…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D64/01322Primary
Electricity · mapped topic
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- What does patent US8993452B2 cover?
- Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment,…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10D64/01322. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).