Selective removal of gate structure sidewall(s) to facilitate sidewall spacer protection

US8993445B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8993445-B2
Application numberUS-201313740343-A
CountryUS
Kind codeB2
Filing dateJan 14, 2013
Priority dateJan 14, 2013
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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Abstract

Official abstract text for this publication.

Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: facilitating fabricating a semiconductor device, the facilitating fabricating comprising: providing a gate structure over at least one fin with at least one layer over the gate structure, the gate structure comprising at least one sidewall; implanting the at least one sidewall with a dopant to form at least one doped region of the gate structure along the at least one sidewall; selectively removing at least a portion of the at least…

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What does patent US8993445B2 cover?
Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure a…
Who is the assignee on this patent?
Globalfoundries Inc, Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10D64/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).