High electron mobility transistor and method for forming the same
US-12176414-B2 · Dec 24, 2024 · US
US8993445B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993445-B2 |
| Application number | US-201313740343-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 14, 2013 |
| Priority date | Jan 14, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.
Opening claim text (preview).
What is claimed is: 1. A method comprising: facilitating fabricating a semiconductor device, the facilitating fabricating comprising: providing a gate structure over at least one fin with at least one layer over the gate structure, the gate structure comprising at least one sidewall; implanting the at least one sidewall with a dopant to form at least one doped region of the gate structure along the at least one sidewall; selectively removing at least a portion of the at least…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.