Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers

US8993405B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8993405-B2
Application numberUS-201414203041-A
CountryUS
Kind codeB2
Filing dateMar 10, 2014
Priority dateAug 18, 2011
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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Abstract

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Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc.) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

First claim

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What is claimed is: 1. A method of forming a capacitor structure, comprising: forming a plurality of lower intermetal dielectric (IMD) layers over a substrate, each of the plurality of lower IMD layers having a first thickness; forming a first metal layer over the plurality of lower IMD layers; forming at least one middle IMD layer over the first metal layer, the at least one middle IMD layer having a second thickness greater than the first thickness; forming a second metal…

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What does patent US8993405B2 cover?
Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. T…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg
What technology area does this patent fall under?
Primary CPC classification H10W20/496. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).