Multi-stack nanosheet structure including semiconductor device
US-2024023326-A1 · Jan 18, 2024 · US
US8993393B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993393-B2 |
| Application number | US-70429610-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 11, 2010 |
| Priority date | Feb 11, 2010 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A structure and method for providing a multiple silicide integration is provided. An embodiment comprises forming a first transistor and a second transistor on a substrate. The first transistor is masked and a first silicide region is formed on the second transistor. The second transistor is then masked and a second silicide region is formed on the first transistor, thereby allowing for device specific silicide regions to be formed on the separate devices.
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a semiconductor device, the method comprising: providing a substrate with a first region and a second region; forming a first type of transistor in the first region, the first type of transistor comprising sidewalls along an outer edge of the first type of transistor; forming a second type of transistor different from the first type of transistor in the second region; forming a first protective layer over the first type of tr…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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