Structure and method to form liner silicide with improved contact resistance and reliablity
US-2015380305-A1 · Dec 31, 2015 · US
Method for fabricating semiconductor device
US8993390B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993390-B2 |
| Application number | US-201414277812-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 15, 2014 |
| Priority date | Apr 26, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.
First claim
Opening claim text (preview).
What is claimed is: 1. A manufacturing method of a semiconductor device, comprising: providing a substrate, with at least one fin structure on the substrate; depositing a metal layer on the fin structure to form a silicide layer; removing the metal layer, wherein no RTP (Rapid Thermal Process) is performed before the metal layer is removed, and; performing a RTP after the metal layer is removed. 2. The manufacturing method of a semiconductor device of…
Assignees
Inventors
Classifications
- H10W20/066Primary
Electricity · mapped topic
Electricity · mapped topic
- H10D30/024Primary
Electricity · mapped topic
- H01L21/76889Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8993390B2 cover?
- A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed aft…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W20/066. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).