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Semiconductor device design method, system and computer program product
US8990762B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990762-B2 |
| Application number | US-201414291285-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 30, 2014 |
| Priority date | Jul 12, 2012 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one second parasitic capacitance among electrical components outside the regions of the plurality of regions. The method further comprises combining, using a netlist generator tool, the extracted first and second parasitic capacitances into a netlist representing the layout. The RC extraction tool is configured to extract the first parasitic capacitances inside at least one region of the plurality of regions using a methodology more accurate than that for extracting the second parasitic capacitances.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device design method performed by at least one processor, said method comprising: extracting, using a resistance and capacitance (RC) extraction tool, a first parasitic capacitance, the first parasitic capacitance being between a first set of electrical components, the first set of electrical components being positioned inside a defined region within a layout of a semiconductor device, the first parasitic capacitance being extracted by the RC…
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Classifications
- G06F30/30Primary
Physics · mapped topic
- G06F30/398Primary
Physics · mapped topic
- G06F17/5081Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8990762B2 cover?
- A semiconductor device design method performed by at least one processor comprises extracting, using a resistance and capacitance (RC) extraction tool, at least one first parasitic capacitance among electrical components inside one or more regions of a plurality of regions in a layout of a semiconductor device. The method also comprises extracting, using the RC extraction tool, at least one sec…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification G06F30/30. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).