Selective cuts to remove predicted interconnect bulging regions
US-2024419882-A1 · Dec 19, 2024 · US
Computer system and method of preparing a layout
US8990751B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990751-B2 |
| Application number | US-91394910-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 28, 2010 |
| Priority date | Oct 28, 2010 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified according to a predetermined maximum value for at least one of an estimated voltage drop along a signal path in the layout or an estimated current density on the signal path. If the at least one layout rule is violated, a violation is indicated.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design, the method comprising: generating a pattern for the layout based on the circuit design; determining, by a processor, if at least one layout rule is violated by the inclusion of the generated pattern in the layout, the at least one layout rule comprising a constraint on a relationship between a power line pattern and a device pattern in the layout, and…
Assignees
Inventors
Classifications
- G06F30/39Primary
Physics · mapped topic
Physics · mapped topic
- G06F30/398Primary
Physics · mapped topic
- G06F17/5068Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8990751B2 cover?
- The present application discloses a method of preparing a layout for manufacturing an integrated circuit chip according to a circuit design. In at least one embodiment, a pattern for the layout based on the circuit design is generated. After the generation of the pattern, it is determined if at least one layout rule is violated in the layout, the at least one layout rule being specified accordi…
- Who is the assignee on this patent?
- Yang Chen-Lin, Chan Wei Min, Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification G06F30/39. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).