Emulator verification system, emulator verification method

US8990624B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8990624-B2
Application numberUS-201113809947-A
CountryUS
Kind codeB2
Filing dateJul 1, 2011
Priority dateJul 13, 2010
Publication dateMar 24, 2015
Grant dateMar 24, 2015

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Abstract

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In order to rapidly perform verification processing on the basis of test patterns in a circuit to be verified, an emulator verification system comprises: an emulator verification device that verifies the normality of content to be executed on the basis of verification test information in a circuit to be verified; a moveable test pattern storage device that is connected to the emulator verification device in an attachable/detachable manner, and that inputs test information for verification processing having a larger volume than a preset data volume into the emulator verification device; and a moveable result pattern storage device that connects to the emulator verification device in an attachable/detachable manner, and that acquires and stores verification results information having a larger volume than a fixed data volume, which shows the results of the verification processing in the emulator verification device.

First claim

Opening claim text (preview).

What is claimed is: 1. An emulator verification system, comprising: a pattern reading/writing device which holds verification test pattern information set in advance and outputs/displays a result of verification processing based on the verification test pattern information; an emulator verification device which performs execution based on the verification test pattern information and verification processing of content of the execution; and a first and a second portable storage medi…

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What does patent US8990624B2 cover?
In order to rapidly perform verification processing on the basis of test patterns in a circuit to be verified, an emulator verification system comprises: an emulator verification device that verifies the normality of content to be executed on the basis of verification test information in a circuit to be verified; a moveable test pattern storage device that is connected to the emulator verificat…
Who is the assignee on this patent?
Nakamura Shin, Nec Corp
What technology area does this patent fall under?
Primary CPC classification G06F11/261. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).