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Integrated circuit system providing enhanced communications between integrated circuit dies and related methods
US8990540B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990540-B2 |
| Application number | US-201213560414-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 27, 2012 |
| Priority date | Jul 28, 2011 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method may include receiving, at a first integrated circuit die, a memory transaction having an address from a second integrated circuit die. The method may further include determining, at the first integrated circuit die and based on the address, if the transaction is for the first integrated circuit die and, if so, translating the address. If transaction is for a third integrated circuit die, the transaction may be transmitted, without modification to the address, to the third integrated circuit die. The translation may be based upon a first table with each entry including a first address and a second translated address corresponding to the first address, and a second table with each entry including a first address and an indication if the transaction is to be forwarded without modification to the address.
First claim
Opening claim text (preview).
What is claimed is: 1. An arrangement comprising: a first interface configured to receive a memory transaction having an address from a second arrangement; a second interface; an address translator configured to determine, based on said address, if said transaction is for said first arrangement and if so to translate said address or if said transaction is for a third arrangement to forward said transaction without modification to said address to said second interface, said sec…
Assignees
Inventors
Classifications
- G06F13/385Primary
Physics · mapped topic
- G06F13/1657Primary
Physics · mapped topic
Physics · mapped topic
- G06F12/1009Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8990540B2 cover?
- A method may include receiving, at a first integrated circuit die, a memory transaction having an address from a second integrated circuit die. The method may further include determining, at the first integrated circuit die and based on the address, if the transaction is for the first integrated circuit die and, if so, translating the address. If transaction is for a third integrated circuit di…
- Who is the assignee on this patent?
- Jones Andrew Michael, Ryan Stuart, St Microelectronics Res & Dev
- What technology area does this patent fall under?
- Primary CPC classification G06F13/385. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).