Pulse-latch based bus design for increased bandwidth
US-2015363352-A1 · Dec 17, 2015 · US
Method for operating memory controller, and memory system including the same
US8990535B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990535-B2 |
| Application number | US-201213564076-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 1, 2012 |
| Priority date | Aug 4, 2011 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method for operating a memory controller capable of controlling a maximum count of a read retry operation is disclosed. The method includes programming a first real time clock (RTC) value indicating a time-of-day when a program operation is performed when the program operation for programming a data to a storage region of a non-volatile memory, obtaining information for the storage region by using the first RTC value read from the non-volatile memory and a second RTC value indicating a time-of-day when a read operation is performed, when the read operation for the data programmed to the storage region is performed, and decreasing a maximum count of a read retry operation by using the information, when the read retry operation is performed for the storage region.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for operating a memory controller comprising: programming a first real time clock (RTC) value indicating a time-of-day associated with a program operation, when the program operation for programming data to a storage region of a non-volatile memory is performed, the first RTC value being programmed into the non-volatile memory; obtaining information for the storage region based on the programmed first RTC value and a second RTC value indicating a…
Assignees
Inventors
Classifications
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F13/16Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8990535B2 cover?
- A method for operating a memory controller capable of controlling a maximum count of a read retry operation is disclosed. The method includes programming a first real time clock (RTC) value indicating a time-of-day when a program operation is performed when the program operation for programming a data to a storage region of a non-volatile memory, obtaining information for the storage region by …
- Who is the assignee on this patent?
- Kim Hyun Seok, Kim Sung Bin, Bae Sung-Hwan, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification G06F13/16. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).