Protection of one-time programmable (OTP) memory

Patent metadata

Field	Value
Publication number	US-8990478-B2
Application number	US-201213555412-A
Country	US
Kind code	B2
Filing date	Jul 23, 2012
Priority date	Jul 23, 2012
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

First claim

What is claimed is:

1. A circuit, comprising:
a first one-time programmable (OTP) memory for receiving a data input for a plurality of address fields; and
a second OTP memory for receiving an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

2. The circuit of claim 1 , wherein a valid data output is provided by the first OTP memory.

3. The circuit of claim 1 , further comprising a logic gate configured to receive a data output of the first OTP memory and a data output of the second OTP memory for verifying that the data output of the first OTP memory is valid.

4. The circuit of claim 1 , wherein the first OTP memory and the second OTP memory receive a same address input.

5. The circuit of claim 1 , wherein the first OTP memory and the second OTP memory receive a same programming input.

6. A one-time programmable (OTP) memory, comprising:
an address input field; and
a data input field,
wherein the data input field receives a data input, and a portion of the address input field receives an inverse of the data input.

7. The OTP memory of claim 6 , further comprising a system for masking a current profile for a programming supply for the OTP memory, such that the data input for the OTP memory is undetectable.

8. The OTP memory of claim 6 , wherein half of the address input field receives the inverse of the data input.

9. A design structure tangibly embodied in a non-transitory machine readable storage medium for designing, manufacturing, or testing a circuit including one-time programmable (OTP) memories, the design structure comprising:
a first one-time programmable (OTP) memory for receiving a data input for a plurality of address fields; and
a second OTP memory for receiving an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

10. The design structure of claim 9 , wherein a valid data output is provided by the first OTP memory.

11. The design structure of claim 9 , further comprising a logic gate configured to receive a data output of the first OTP memory and a data output of the second OTP memory for verifying that the data output of the first OTP memory is valid.

12. The design structure of claim 9 , wherein the first OTP memory and the second OTP memory receive a same address input and a same programming input.

13. The design structure of claim 9 , wherein the design structure comprises a netlist.

14. The design structure of claim 9 , wherein the design structure resides on the storage medium in a data format used for the exchange of layout data of integrated circuits.

Assignees

• Fifield John A
• Pomichter Jr Gerald P
• Zimmerman Jeffrey S
• IBM

Inventors

• Fifield John A
• Pomichter Jr Gerald P
• Zimmerman Jeffrey S

Classifications

• G11C7/24 Primary

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G06F12/1458 Primary

  by checking the subject access rights · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C8/20

  Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access · CPC title