Header circuit for controlling supply voltage of a cell

Patent metadata

Field	Value
Publication number	US-8988949-B2
Application number	US-201213633222-A
Country	US
Kind code	B2
Filing date	Oct 2, 2012
Priority date	Oct 2, 2012
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

One or more techniques or systems for controlling a supply voltage of a cell are provided herein. Additionally, one or more techniques or systems for mitigating leakage of the cell are provided. In some embodiments, a header circuit is provided, including a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor including a first gate, a first source, and a first drain. Additionally, the header circuit includes a second pull-down PMOS transistor including a second gate, a second source, and a second drain. In some embodiments, the first drain of the first pull-up PMOS transistor is connected to the second source of the second pull-down PMOS transistor and a supply voltage line for one or more cells. In this manner, a pull-down PMOS is configured to control the supply voltage of the cell, thus facilitating voltage control for a write assist, for example.

First claim

What is claimed is:

1. A header circuit for controlling a supply voltage for a cell, comprising:
a first pull-up p-type metal-oxide-semiconductor (PMOS) transistor, the first pull-up PMOS transistor comprising a first gate, a first source, and a first drain;
a pull-up control unit configured to control biasing for the first gate of the first pull-UP PMOS transistor based on a shut down signal, a bank select signal, and a write mux signal, the shut down signal corresponding to a…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Hua Chung-Hsien
• Wu Chung-Yi
• Yang Chen-Lin
• Lee Cheng Hung

Classifications

• G11C11/417 Primary

  Physics · mapped topic