MIM capacitor with lower electrode extending through a conductive layer to an STI

Patent metadata

Field	Value
Publication number	US-8987086-B2
Application number	US-201213555831-A
Country	US
Kind code	B2
Filing date	Jul 23, 2012
Priority date	Mar 4, 2009
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

First claim

What is claimed is:

1. A method comprising:
providing a semiconductor substrate having an isolation structure disposed in the semiconductor substrate;
forming a conductive layer over the isolation structure;
forming a trench extending through the conductive layer and to a top surface of the isolation structure wherein the trench has a bottommost surface that extends to at least the top surface of the isolation structure;
forming a bottom metal layer directly on the bottommost surface of the trench such that the bottom metal layer physically contacts the isolation structure at the bottommost surface of the trench, wherein the bottom metal layer physically contacts the conductive layer;
forming a dielectric layer over the bottom metal layer within the trench, wherein the conductive layer is disposed over the isolation structure during the forming of the dielectric layer over the bottom metal layer within the trench; and
forming a top metal layer over the dielectric layer within the trench.

2. The method of claim 1 , further comprising forming a silicide layer over the conductive layer prior to forming the trench extending through the conductive layer and to the top surface of the isolation structure.

3. The method of claim 1 , wherein the conductive layer includes a doped polysilicon layer and the bottom metal layer physically contacts the doped polysilicon layer.

4. The method of claim 1 , further comprising after forming the trench, performing an etching process that modifies a corner profile of the trench.

5. The method of claim 1 , wherein the isolation structure is a shallow trench isolation structure.

6. The method of clam 1 , wherein the bottommost surface of the trench is embedded within the isolation structure.

7. A method comprising:
providing a semiconductor substrate having an isolation structure disposed in the semiconductor substrate;
forming a conductive layer over the isolation structure;
forming an interlayer dielectric layer over the conductive layer;
forming a first trench extending through the interlayer dielectric layer, conductive layer, and to the isolation structure, wherein the first trench has a bottommost surface defined by the isolation structure;
forming a bottom metal layer within the first trench directly on the bottommost surface of the first trench such that the bottom metal layer physically contacts the isolation structure at the bottommost surface of the first trench, wherein the bottom metal layer physically contacts the conductive layer;
forming a dielectric layer over the bottom metal layer within the first trench, wherein the conductive layer is disposed over the isolation structure during the forming of the dielectric layer over the bottom metal layer within the first trench; and
forming a top metal layer over the dielectric layer within the first trench.

8. The method of claim 7 , further comprising forming an etch stop layer over the semiconductor substrate prior to forming the interlayer dielectric layer over the conductive layer.

9. The method of claim 7 , further comprising forming an etch stop layer over the interlayer dielectric layer.

10. The method of claim 9 , further comprising forming another interlayer dielectric layer over the etch stop layer.

11. The method of claim 10 , further comprising performing a first etching process that stops at the etch stop layer to form a second trench.

12. The method of claim 11 , wherein forming the first trench extending through the interlayer dielectric layer, conductive layer, and to the isolation structure occurs after performing the first etching process.

13. The method of claim 7 , wherein forming the first trench extending through the interlayer dielectric layer, conductive layer, and to the isolation structure includes the first trench extending through a portion of the isolation structure.

14. The method of claim 7 , further comprising:
forming a contact feature within the interlayer dielectric layer, wherein the contact feature is coupled to a doped feature of a gate structure;
forming another interlayer dielectric layer over the interlayer dielectric layer; and
forming a second trench in the another interlayer dielectric layer that extends to the contact feature, and
wherein forming the bottom metal layer within the first trench includes forming the bottom layer within the second trench,
wherein forming the dielectric layer over the bottom metal layer within the first trench includes forming the dielectric layer over the bottom metal layer within the second trench, and
wherein forming the top metal layer over the dielectric layer within the first trench includes forming the top metal layer over the dielectric layer within the second trench.

15. A method of fabricating a semiconductor device that includes a semiconductor substrate including a first region and a second region, the first region including an isolation structure and a conductive layer disposed over the isolation structure, the second region including a memory cell that includes a transistor having a doped feature, the method comprising:
forming a first interlayer dielectric (ILD) layer over the conductive layer in the first region and over the memory cell in the second region;
forming a contact feature within the first ILD layer in the second region, the contact feature being coupled to the doped feature of the transistor; and
forming a second ILD layer over the first ILD layer in first and second regions;
forming a first trench that extends at least to the conductive layer in the first region and a second trench that extends to the contact feature in the second region;
forming a bottom metal layer over the second ILD partially filling in the first and second trenches;
removing portions of the bottom metal layer outside of the first and second trenches;
forming a dielectric layer over the second ILD layer partially filling in the first and second trenches; and
forming a top metal layer over the dielectric layer partially filling in the first and second trenches,
wherein the first trench extends through the conductive layer and at least to the isolation structure.

16. The method of claim 15 , further comprising:
forming an etch stop layer over the first ILD layer in the first and second regions after forming the contact feature; and
removing the etch stop layer in the first region;
wherein forming the first trench and the second trench includes:
performing a dry etching process that stops at least at the conductive layer in the first region thereby forming the first trench and that stops at the etch stop layer in second region thereby forming the second trench; and
removing the exposed etch stop layer in the second trench.

17. The method of claim 15 , further comprising:
forming an etch stop layer over the first ILD layer in the first and second regions after forming the contact feature;
wherein forming the first trench and the second trench includes:
performing a first dry etching that stops at the etch stop layer thereby forming a portion of the first trench and a portion of the second trench;
removing the exposed etch stop layer in the portion of the first trench and in the portion of the second trench, respectively;
forming a protection layer filling in the second trench;
performing a second dry etching that stops at least at the conductive layer in the first region thereby extending the portion of the first trench.

18. The method of claim 15 , wherein the first trench extends through the conductive layer and through a portion of the isolation

Assignees

• Ching Kuo-Cheng
• Tu Kuo-Chi
• Chen Chun-Yao
• Taiwan Semiconductor Mfg

Inventors

• Ching Kuo-Cheng
• Tu Kuo-Chi
• Chen Chun-Yao

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H10D84/212 Primary

  of only capacitors · CPC title