Thin film transistor and fabricating method

Patent metadata

Field	Value
Publication number	US-8987071-B2
Application number	US-201314107742-A
Country	US
Kind code	B2
Filing date	Dec 16, 2013
Priority date	Dec 21, 2011
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

A thin-film transistor comprises a semiconductor panel, a dielectric layer, a semiconductor film layer, a conduct layer, a source and a drain. The semiconductor panel comprises a base, an intra-dielectric layer, at least one metal wire layer and at least one via layer. The dielectric layer is stacked on the semiconductor panel. The semiconductor film layer is stacked on the dielectric layer. The conduct layer is formed on the semiconductor film layer. The source is formed on the via of the vias that is adjacent to and connects to the gate via. The drain is formed on another via of the vias that is adjacent to and connects to the gate via. A fabricating method for a thin-film transistor with metal-gates and nano-wires is also disclosed.

First claim

What is claimed is:

1. A fabricating method for a thin-film transistor being used in a semiconductor panel consisting of a base, an intra-dielectric layer, at least one metal wire layer, at least one via layer and a surface, the intra-dielectric layer being stacked on the base, the at least one metal wire layer comprising a lowest metal wire layer and at least one metal wire with multiple metal wires being separated by corresponding intra-dielectric layers, one metal wire of the metal wires is a metal wire gate, the at least one via layer being stacked on the at least one metal wire layer and comprising at least one via with multiple vias being separated by corresponding intra-dielectric layers, wherein each via being stacked on the one metal wire of the metal wires, of which one via being stacked on the metal wire gate being a gate via, comprising steps of:
grinding the surface of the semiconductor panel;
etching one via layer of the at least one via layer;
stacking a dielectric layer on the semiconductor panel;
stacking a semiconductor film layer on the dielectric layer;
forming a conduct layer on the semiconductor film layer;
defining a source zone and a drain zone each on a via of the vias that is adjacent to the gate via and connecting to the source zone, the drain zone and the gate via;
forming two generally U-shaped nano-wire channels in the gate via respectively connecting the source to the drain along a plane parallel with the base; and

activating the conduct layer under the source and the drain.

2. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein the base further comprises:
at least one complementary metal-oxide-semiconductor well;
at least one poly-silicon thin film transistor being stacked on the complementary metal-oxide-semiconductor well;
at least one shallow trench isolation unit separating the complementary metal-oxide-semiconductor well and separating the at least one poly-silicon thin film transistor; and
at least one contact channel connecting the at least one poly-silicon thin film transistor and the lowest metal wire layer.

3. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein the dielectric layer is selected from a group consisting of an oxide-nitride-oxide layer, an oxide layer, an oxide-nitride layer, a nitride layer and a high K layer.

4. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein the grinding step grinding the surface of the semiconductor panel is performed by chemical mechanical polishing.

5. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein stacking a semiconductor film layer step is performed by a technique selected from a group consisting of low temperature chemical vapor deposition and very high frequency plasma enhanced chemical vapor deposition (VHFPECVD).

6. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein the etching step is performed by over etching.

7. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein forming a conduct layer step is performed by a technique selected from a group consisting of ion doping, depositing a silicide layer and in-situ doping.

8. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein forming the source and the drain and forming the two nano-wire channels step is performed by forming two spacer nanowires in the gate via through dry etching.

9. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein the activating the conduct layer step is performed by low temperature annealing under 500° C.

10. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein the activating the conduct layer step is performed by low temperature laser annealing under 500° C.

11. The fabricating method for a thin-film transistor as claimed in claim 1 , wherein the semiconductor film layer is selected from a group consisting of silicon film layer, germanium film layer and silicon-germanium film layer.

12. A method for fabricating a thin-film transistor, wherein a gate via is electrically connected to a metal wire gate and formed in an intra-dielectric layer stacked on a substrate, the method comprising:
etching the gate via to form a gate recess between the gate via and a surface of the intra-dielectric layer;
forming a dielectric layer, a semiconductor film layer, and a conductor layer on the gate recess and the intra-dielectric layer;
forming a source pad and a drain pad adjacent to the gate recess by etching the conductor layer and the semiconductor film layer adjacent to the gate recess; and etching a portion of the conductor layer and the semiconductor film layer on the dielectric layer of the gate recess to form a first nano-wire channel and a second nano-wire channel connected between the source pad and the drain pad along a plane parallel with the substrate, wherein the first nano-wire channel and the second nano-wire channel are generally U-shaped and located in the gate via on two opposite sides of the gate recess.

13. The method for fabricating a thin-film transistor as claimed in claim 12 , further comprises activating the conduct layer under the source pad and the drain pad by low temperature annealing, low temperature laser annealing or microwave annealing under 500° C.

14. The method for fabricating a thin-film transistor as claimed in claim 12 , wherein the first nano-wire channel and the second nano-wire channel are spacer nano-wires.

15. The method for fabricating a thin-film transistor as claimed in claim 12 , wherein the semiconductor film layer is selected from a group consisting of silicon film layer, germanium film layer and silicon-germanium film layer.

16. The method for fabricating a thin-film transistor as claimed in claim 12 , wherein the dielectric layer is selected from a group consisting of an oxide-nitride-oxide layer, an oxide layer, an oxide-nitride layer, a nitride layer and a high K layer.

17. A method for fabricating a thin-film transistor, wherein a gate via is electrically connected to a metal wire gate and formed in an intra-dielectric layer stacked on a substrate, the method comprising:
etching the gate via to form a gate recess between the gate via and a surface of the intra-dielectric layer;
forming a dielectric layer, a semiconductor film layer, and a conductor layer on the gate recess and the intra-dielectric layer; and
etching a portion of the conductor layer and the semiconductor film layer on the dielectric layer of the gate recess to form a first nano-wire channel and a second nano-wire channel connected between a source pad and the drain pad adjacent to the gate recess and along a plane parallel with the substrate;
wherein the first nano-wire channel and the second nano-wire channel are generally U-shaped and located in the gate via on two opposite sides of the gate recess.

18. The method for fabricating a thin-film transistor as claimed in claim 17 , wherein the method further comprises:
forming the source pad and the drain pad by patterned etching the conductor layer and the semiconductor film layer adjacent to the gate recess.

19. The method for fabricating a thin-film transistor as claimed in claim 17 , further comprises activating the conduct layer under the source pad and the drain pad by low temperature annealing, low temperature laser annealing or microwave annealing under 500° C.

20. The method for fabricating a thin-film transistor as cl

Assignees

• Nat Applied Res Laboratories

Inventors

• Chen min-cheng
• Lin Chang-Hsien
• Lin Chia-Yi
• Lai Tung-Yen
• Ho Chia-Hua

Classifications

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/122

  oriented at angles to substrates, e.g. perpendicular to substrates · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title