Systems and methods of testing memory devices
US-2024387303-A1 · Nov 21, 2024 · US
US8987014B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8987014-B2 |
| Application number | US-46709409-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 15, 2009 |
| Priority date | May 21, 2008 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each interconnect bump pad and proximate sacrificial bump pad. The sacrificial bump pads, interconnect bump pads, and conductive link are formed concurrently or during bump formation. The wafer is electrically tested by contacting the sacrificial bump pads. The electrical test identifies known good die and defective die. The sacrificial bump pads and a portion of the conductive link are removed after wafer probing. Bumps are formed over the interconnect bump pads. The semiconductor wafer can be sold or transferred to a third party after wafer probing without bumps.
Opening claim text (preview).
What is claimed: 1. A method of making a semiconductor device, comprising: providing a semiconductor wafer including a plurality of semiconductor die; forming a plurality of interconnect bump pads over the semiconductor die; forming a plurality of sacrificial bump pads in proximity to the interconnect bump pads and over an active surface of the semiconductor die; forming a conductive link between each interconnect bump pad and proximate sacrificial bump pad; wafer probing…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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