Semiconductor wafer and method of forming sacrificial bump pad for wafer probing during wafer sort test

US8987014B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8987014-B2
Application numberUS-46709409-A
CountryUS
Kind codeB2
Filing dateMay 15, 2009
Priority dateMay 21, 2008
Publication dateMar 24, 2015
Grant dateMar 24, 2015

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Abstract

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A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each interconnect bump pad and proximate sacrificial bump pad. The sacrificial bump pads, interconnect bump pads, and conductive link are formed concurrently or during bump formation. The wafer is electrically tested by contacting the sacrificial bump pads. The electrical test identifies known good die and defective die. The sacrificial bump pads and a portion of the conductive link are removed after wafer probing. Bumps are formed over the interconnect bump pads. The semiconductor wafer can be sold or transferred to a third party after wafer probing without bumps.

First claim

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What is claimed: 1. A method of making a semiconductor device, comprising: providing a semiconductor wafer including a plurality of semiconductor die; forming a plurality of interconnect bump pads over the semiconductor die; forming a plurality of sacrificial bump pads in proximity to the interconnect bump pads and over an active surface of the semiconductor die; forming a conductive link between each interconnect bump pad and proximate sacrificial bump pad; wafer probing…

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What does patent US8987014B2 cover?
A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each i…
Who is the assignee on this patent?
Pendse Rajendra D, Stats Chippac Ltd
What technology area does this patent fall under?
Primary CPC classification H10P74/273. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).