Memory system and host device
US-2024394189-A1 · Nov 28, 2024 · US
US8984239B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8984239-B2 |
| Application number | US-201314020304-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 6, 2013 |
| Priority date | Oct 24, 2008 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described.
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What is claimed is: 1. A processor comprising: a control component that enforces ordering and atomicity of memory writes; a memory component to enforce timing restraints in addition to the ordering and the atomicity enforced by the control component; a non-volatile memory that is addressable by the control component; and a dynamic random access memory (DRAM), which shares an address space with the non-volatile memory; wherein the memory component comprises: a scheduler c…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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