Hardware and operating system support for persistent memory on a memory bus

US8984239B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8984239-B2
Application numberUS-201314020304-A
CountryUS
Kind codeB2
Filing dateSep 6, 2013
Priority dateOct 24, 2008
Publication dateMar 17, 2015
Grant dateMar 17, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described.

First claim

Opening claim text (preview).

What is claimed is: 1. A processor comprising: a control component that enforces ordering and atomicity of memory writes; a memory component to enforce timing restraints in addition to the ordering and the atomicity enforced by the control component; a non-volatile memory that is addressable by the control component; and a dynamic random access memory (DRAM), which shares an address space with the non-volatile memory; wherein the memory component comprises: a scheduler c…

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Frequently asked questions

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What does patent US8984239B2 cover?
Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described.
Who is the assignee on this patent?
Microsoft Corp, Microsoft Technology Licensing Llc
What technology area does this patent fall under?
Primary CPC classification G06F12/0804. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).