Semiconductor device
US-2024321938-A1 · Sep 26, 2024 · US
Combinatorial optimization of interlayer parameters
US8980653B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8980653-B2 |
| Application number | US-201213622750-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 19, 2012 |
| Priority date | Sep 19, 2012 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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Abstract
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The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.
First claim
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What is claimed: 1. A method of combinatorial optimization of interlayer parameters, the method comprising: depositing a first electrode on a substrate; combinatorially forming a plurality of interlayers on separate site isolated regions of the first electrode, the plurality of interlayers being formed based on at least one sequentially altered parameter; depositing a bulk oxide layer across the plurality of interlayers; determining a change in thickness of the first electro…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D1/68Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8980653B2 cover?
- The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the elect…
- Who is the assignee on this patent?
- Ananthan Venkat, Intermolecular Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D1/68. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).