IC with connections between linking module and test access ports

Patent metadata

Field	Value
Publication number	US-8977918-B2
Application number	US-201414460824-A
Country	US
Kind code	B2
Filing date	Aug 15, 2014
Priority date	Aug 30, 1996
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

First claim

What is claimed is:

1. An integrated circuit comprising:
(A) a test data in lead, a test clock lead, a test mode select lead, and a test data out lead;
(B) a first test access port having:
a first test data in input, a first test clock input, a first test mode select input, and a first test data out output;
a first data register coupled between the first data in input and the first data out output;
a first instruction register coupled between the first data in input and the…

Assignees

• Texas Instruments Inc

Inventors

• Haroun Baher S
• Whetsel Lee D

Classifications

• G01R31/3177 Primary

  Physics · mapped topic

• G11C29/46

  Physics · mapped topic

• G01R31/318536

  Physics · mapped topic

• G01R31/318555 Primary

  Physics · mapped topic

• G01R31/2851

  Physics · mapped topic