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Multi-input and binary reproducible, high bandwidth floating point adder in a collective network
US8977669B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8977669-B2 |
| Application number | US-68477610-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 8, 2010 |
| Priority date | Jan 8, 2010 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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- Title
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Abstract
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To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.
First claim
Opening claim text (preview).
What is claimed is: 1. A parallel computing system for adding a plurality of first floating point numbers, the system comprising: a plurality of computing nodes, a computing node including at least one processor and at least one memory device; and a collective logic device including: a front-end logic device for receiving a plurality of the first floating point numbers in parallel from the computing nodes or network links and for converting the first floating point numbers to a…
Assignees
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Classifications
- G06F9/30014Primary
Physics · mapped topic
Physics · mapped topic
- G06F7/38Primary
Physics · mapped topic
- G06F9/3885Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8977669B2 cover?
- To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floati…
- Who is the assignee on this patent?
- Chen Dong, Eisley Noel A, Heidelberger Philip, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/30014. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).