Systems and methods of testing memory devices
US-2024387303-A1 · Nov 21, 2024 · US
US8976574B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8976574-B2 |
| Application number | US-201313799408-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2013 |
| Priority date | Mar 13, 2013 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit, comprising: a plurality of bit-cells arranged to store data; and a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner, wherein the sensor comprises two cross-coupled inverters, each of the cross-coupled inverters comprising a p-channel pull-up transistor and an n-channel pull-down transistor, a first access transistor configured to connect a first bit-line to an input of…
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