Memory with fly-bitlines that work with single-ended sensing and associated memory access method
US-2024233786-A9 · Jul 11, 2024 · US
Semiconductor apparatus
US8976567B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8976567-B2 |
| Application number | US-201213720706-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 19, 2012 |
| Priority date | Aug 17, 2012 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and second bank groups; and a read operation controller arranged adjacent to any one of the first and second bank groups and configured to control read operations of the first and second bank groups.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor apparatus having a core area and a peripheral area, comprising: a first bank group including a plurality of banks stacked with each other and arranged at the core area, wherein the plurality of banks of the first bank group are arranged in a first direction; a second bank group including a plurality of banks stacked with each other and arranged at the core area, wherein the plurality of banks of the second bank group are arranged in the fir…
Assignees
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Classifications
Physics · mapped topic
- G11C7/18Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8976567B2 cover?
- A semiconductor apparatus includes: a first bank group comprising a plurality of first banks; a second bank group comprising a plurality of second banks arranged adjacent to the first bank group; a write operation controller arranged between the first and second bank groups so as to be adjacent to the first and second bank groups, and configured to control write operations of the first and seco…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C7/18. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).