Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-8976563-B2
Application number	US-201313900282-A
Country	US
Kind code	B2
Filing date	May 22, 2013
Priority date	Dec 20, 2010
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

In a memory device having a hierarchical bit line architecture, a main memory array is divided into two sub-memory arrays. The number of sub bit lines is twice the number of main bit lines, and global data lines are formed in the same metal interconnect layer as the main bit lines, thereby reducing an increase in the number of interconnects used in a memory macro. Furthermore, after charge sharing of the bit lines, the global data lines are kept in a pre-charge state at the time of amplification using sense amplifiers so that the global data lines function as shields of the main bit lines. This largely reduces interference noise between adjacent main bit lines to improve operating characteristics.

First claim

What is claimed is:

1. A semiconductor memory device having a hierarchical bit line architecture, the semiconductor memory device comprising:
a first sub-memory array including a plurality of memory cells coupled in common to first sub bit lines in a cross-point manner;
a second sub-memory array including a plurality of memory cells coupled in common to second sub bit lines in a cross-point manner;
main bit lines including a first main bit line and a second main bit line, the…

Assignees

• Panasonic Corp

Inventors

• Iida Masahisa

Classifications

• G11C11/4091 Primary

  Physics · mapped topic

• G11C7/18

  Physics · mapped topic

• G11C5/06 Primary

  Physics · mapped topic

• G11C11/4097

  Physics · mapped topic

• G11C5/066

  Physics · mapped topic