Structure to reduce chip shift during assembly
US-2024395758-A1 · Nov 28, 2024 · US
Wafer level package, chip size package device and method of manufacturing wafer level package
US8975736B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8975736-B2 |
| Application number | US-201114000111-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 16, 2011 |
| Priority date | Feb 16, 2011 |
| Publication date | Mar 10, 2015 |
| Grant date | Mar 10, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A wafer level package has a first wafer having a plurality of chips mounted or formed thereon in a plane, and a second wafer that is opposed to the first wafer. The first wafer and the second wafer are joined while a seal frame that seals a periphery of each chip is interposed therebetween. A gap is formed between the seal frames of the chips adjacent to each other. A partial connect part that partially connects the seal frames to each other is provided in the gap formed between the seal frames of the chips adjacent to each other.
First claim
Opening claim text (preview).
The invention claimed is: 1. A wafer level package comprising: a first wafer comprising a plurality of chips mounted or formed thereon in a plane; and a second wafer that is opposed to the first wafer, wherein the first wafer and the second wafer are joined while a plurality of partially connected seal frames that seal a periphery of each chip is interposed therebetween, wherein a gap is formed between the seal frames of the chips adjacent to each other, and wherein a part…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8975736B2 cover?
- A wafer level package has a first wafer having a plurality of chips mounted or formed thereon in a plane, and a second wafer that is opposed to the first wafer. The first wafer and the second wafer are joined while a seal frame that seals a periphery of each chip is interposed therebetween. A gap is formed between the seal frames of the chips adjacent to each other. A partial connect part that …
- Who is the assignee on this patent?
- Okuno Toshiaki, Inoue Katsuyuki, Fujiwara Takeshi, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10W95/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).