Wafer level package, chip size package device and method of manufacturing wafer level package
US-8975736-B2 · Mar 10, 2015 · US
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Inoue Katsuyuki patents
Inoue Katsuyuki holds 1 patent in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 1 |
| Recent patents | 0 |
| First publication | Mar 10, 2015 |
| Latest publication | Mar 10, 2015 |
Filing trend
Year-over-year patent counts for this assignee.
Not enough yearly data to assess filing trend yet.
| Year | Patents |
|---|---|
| 2015 | 1 |
| Year | Patents |
|---|---|
| 2015 | 1 |
Recent patents
Latest publications where this party is an assignee.
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| H10W90/734 | 1 |
| H10W72/07352 | 1 |
| H10W72/07337 | 1 |
| H10W72/07336 | 1 |
| H10W72/01938 | 1 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Operations & Transport | 1 |
| Electricity | 1 |