Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar
US-2024419761-A1 · Dec 19, 2024 · US
Semiconductor memory device
US8971092B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8971092-B2 |
| Application number | US-201314021052-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 9, 2013 |
| Priority date | Feb 28, 2013 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch in a first direction perpendicular to a substrate and extend in a second direction parallel to the substrate. The second wiring lines are arranged at a second pitch in the second direction and extend in the first direction. The control circuit is configured to change voltages applied to a selected first wiring line according to the positions of the selected first wiring lines in the first direction.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device comprising: a memory cell array comprising first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, memory cells having a variable resistance element; and a control circuit configured to control voltages of selected first and second wiring lines, the first wiring lines being arranged at a first pitch in a…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G11C13/0007Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8971092B2 cover?
- A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines. The first wiring lines are arranged at a first pitch …
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification G11C13/0007. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).