Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-8971090-B2
Application number	US-201313773989-A
Country	US
Kind code	B2
Filing date	Feb 22, 2013
Priority date	Aug 31, 2012
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A semiconductor memory device according to an embodiment comprises: a memory cell array including memory cells, each of the memory cells disposed at each of intersections of first lines and second lines and including a variable resistor; and a control circuit configured to apply a first voltage to a selected first line and to apply a second voltage having a voltage value which is smaller than that of the first voltage to a selected second line, such that a selected memory cell is applied with a first potential difference required in an operation of the selected memory cell. The control circuit is configured such that when the first potential difference is applied a plurality of times to a plurality of the selected memory cells to execute the operation, the number of selected memory cells simultaneously applied with the first potential difference can be changed.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a plurality of first lines disposed on a substrate;
a plurality of second lines disposed intersecting the first lines;
a memory cell array including memory cells, each of the memory cells disposed at each of intersections of the first lines and the second lines and including a variable resistor; and
a control circuit configured to apply a first voltage to a selected first line and to apply a second voltage hav…

Assignees

• Toshiba Kk

Inventors

• Tsukamoto Takayuki
• Nishimura Jun
• Une Masahiro
• Shimotori Takafumi
• Minemura Yoichi
• Kanno Hiroshi

Classifications

• G11C2013/0088

  Physics · mapped topic

• G11C13/0061

  Physics · mapped topic

• G11C13/0002

  Physics · mapped topic

• G11C13/0069 Primary

  Physics · mapped topic