Capacitorless DRAM on bulk silicon

Patent metadata

Field	Value
Publication number	US-8971086-B2
Application number	US-201313918378-A
Country	US
Kind code	B2
Filing date	Jun 14, 2013
Priority date	Jun 8, 2005
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

First claim

We claim:

1. A method of operating a capacitorless DRAM of a memory chip, the method comprising:
placing a floating body in a first state; and
detecting the first state by measuring a first current at a source of the capacitorless DRAM;
wherein the floating body is defined within a localized silicon-over-insulator, wherein the localized silicon-over-insulator is positioned over a-localized insulator layer, and wherein the insulator layer is laterally surrounded by silicon and…

Assignees

• Micron Technology Inc

Inventors

• Mathew Suraj
• Trivedi Jigish D

Classifications

• H10D86/201

  Electricity · mapped topic

• H10D30/711

  Electricity · mapped topic

• H10B12/20

  Electricity · mapped topic

• H10D86/01 Primary

  Electricity · mapped topic

• H10B12/01 Primary

  Electricity · mapped topic