Semiconductor memory device including alignment key structures

US8970050B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8970050-B2
Application numberUS-201213728549-A
CountryUS
Kind codeB2
Filing dateDec 27, 2012
Priority dateAug 17, 2012
Publication dateMar 3, 2015
Grant dateMar 3, 2015

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Abstract

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A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.

First claim

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What is claimed is: 1. A semiconductor memory device comprising: a first semiconductor chip including a first region and a second region wherein the second region is positioned in an edge of the first semiconductor chip; a second semiconductor chip including a third region corresponding to the first region and a fourth region, wherein the fourth region is positioned in an edge of the second semiconductor chip which corresponds to the second region, and stacked on top of the firs…

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What does patent US8970050B2 cover?
A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).