Electronic device and manufacturing method thereof
US-2024404831-A1 · Dec 5, 2024 · US
Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
US8970044B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8970044-B2 |
| Application number | US-201113167631-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 23, 2011 |
| Priority date | Jun 23, 2011 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
Official abstract text for this publication.
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral vertical conductor directly on the peripheral non-horizontal conductive plate and the substrate.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacture of an integrated circuit packaging system comprising: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; attaching a heat slug to the integrated circuit; forming an interior non-vertical conductive plate coplanar with the heat slug, surrounding the heat slug, and above the integrated circuit…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8970044B2 cover?
- A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate; forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation interior sidewall; forming a peripheral non-horizontal conductive plate directly on the encapsulation interior sidewall; and forming a peripheral verti…
- Who is the assignee on this patent?
- Choi A Leam, Park Dongsam, Lee Yongduk, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W74/016. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).