Bump structures for semiconductor package

US8970035B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8970035-B2
Application numberUS-201213624356-A
CountryUS
Kind codeB2
Filing dateSep 21, 2012
Priority dateAug 31, 2012
Publication dateMar 3, 2015
Grant dateMar 3, 2015

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Abstract

Official abstract text for this publication.

A package structure includes a first substrate bonded to a second substrate by Connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.

First claim

Opening claim text (preview).

What is claimed is: 1. A package structure, comprising: a first substrate having a first region and a second region and comprising a metal pad overlying the first substrate in the first region, a first metal pillar overlying the metal pad, a passivation layer overlying the first substrate in the second region, and a second metal pillar in the second region, wherein the first metal pillar extends through the passivation layer and has a bottommost surface below a top surface of the…

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What does patent US8970035B2 cover?
A package structure includes a first substrate bonded to a second substrate by Connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrat…
Who is the assignee on this patent?
Lin Jing-Cheng, Tsai Po-Hao, Taiwan Semiconductor Mfg
What technology area does this patent fall under?
Primary CPC classification H10W72/072. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).