Semiconductor integrated circuit apparatus and method of manufacturing the same
US-9224832-B2 · Dec 29, 2015 · US
Isolation structures and methods of forming the same
US8969997B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969997-B2 |
| Application number | US-201213676434-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 14, 2012 |
| Priority date | Nov 14, 2012 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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A method of forming of a semiconductor structure has isolation structures. A substrate having a first region and a second region is provided. The first region and the second region are implanted with neutral dopants to form a first etching stop feature and a second stop feature in the first region and the second region, respectively. The first etching stop feature has a depth D 1 and the second etching stop feature has a depth D 2 . D 1 is less than D 2 . The substrate in the first region and the second region are etched to form a first trench and a second trench respectively. The first trench and the second trench land on the first etching stop feature and the second etching stop feature, respectively.
First claim
Opening claim text (preview).
What is claimed: 1. A method of forming a semiconductor structure having isolation structures, the method comprising: providing a substrate having a first region and a second region; implanting the first region and the second region with neutral dopants to form a first etching stop feature and a second stop feature in the first region and the second region, respectively, the first etching stop feature having a depth D 1 , and the second etching stop feature having a depth D 2 ,…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W10/0143Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8969997B2 cover?
- A method of forming of a semiconductor structure has isolation structures. A substrate having a first region and a second region is provided. The first region and the second region are implanted with neutral dopants to form a first etching stop feature and a second stop feature in the first region and the second region, respectively. The first etching stop feature has a depth D 1 and the secon…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W10/0143. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).