Apparatus and method for making a secured substrate
US-2024355722-A1 · Oct 24, 2024 · US
Semiconductor chip package and method
US8969985B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969985-B2 |
| Application number | US-201113221607-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 30, 2011 |
| Priority date | Aug 30, 2011 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by an isolation layer, a first external pad, and a via contact contacting the current rail with the first external pad.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device package comprising: a substrate; a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material; a current rail adjacent the semiconductor chip, wherein the current rail is isolated from the semiconductor chip by an isolation layer, and wherein the current rail comprises a bottleneck; a first external pad; and a via contact contacting the current rail with the first external pad.…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969985B2 cover?
- A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by…
- Who is the assignee on this patent?
- Strutz Volker, Landau Stefan, Ausserlechner Udo, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W76/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).