Semiconductor integrated circuit device having reservoir capacitor and method of manufacturing the same
US-2015357377-A1 · Dec 10, 2015 · US
Method and structure for forming on-chip high quality capacitors with ETSOI transistors
US8969938B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969938-B2 |
| Application number | US-201414154202-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 14, 2014 |
| Priority date | Dec 12, 2011 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination of which is accompanied with appropriate etch.
First claim
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What is claimed is: 1. A semiconductor structure, comprising: an SOI (semiconductor on insulator) substrate comprising a base substrate, a doped back gate layer on the base substrate, a buried insulating layer on the doped back gate layer and an ETSOI (extra thin SOI) layer on the buried insulating layer, said SOI substrate divided into a transistor region and a capacitor region, the transistor region and the capacitor region each having the doped back gate layer, the buried insul…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8969938B2 cover?
- An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography duri…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D1/047. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).