Transistor contacts and methods of forming the same
US-2024395871-A1 · Nov 28, 2024 · US
US8969932B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969932-B2 |
| Application number | US-201213711779-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 12, 2012 |
| Priority date | Dec 12, 2012 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.
Opening claim text (preview).
What is claimed: 1. A method of forming a device in and above a semiconducting substrate, comprising: prior to forming an isolation region in said substrate for said device, forming a doped well region and a doped punch-stop region in said substrate; introducing dopant material into said substrate to form a dopant-containing layer proximate an upper surface of said substrate, wherein said dopant material is adapted to retard diffusion of boron or phosphorous; performing an epi…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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