Field effect transistors and method of forming the same

US8969922B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8969922-B2
Application numberUS-201213368960-A
CountryUS
Kind codeB2
Filing dateFeb 8, 2012
Priority dateFeb 8, 2012
Publication dateMar 3, 2015
Grant dateMar 3, 2015

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  2. Abstract

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  5. First independent claim

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Abstract

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A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device disposed in a second device region, the second device including a second gate structure, second gate spacers formed on the sidewalls of the second gate structure, and second source and drain features. The semiconductor device further includes a contact etch stop layer (CESL) disposed on the first and second gate spacers and interconnect structures disposed on the first and second source and drain features. The interconnect structures are in electrical contact with the first and second source and drain features and in contact with the CESL.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a semiconductor substrate including a first device region, a second device region, a third device region, a region between the first and second device regions, and a shallow trench isolation (STI) feature between the second and third device regions; a first device of a first type disposed in the first device region, the first device of the first type including a first gate structure, first gate spacers formed on the sidew…

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What does patent US8969922B2 cover?
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including a first device disposed in a first device region, the first device including a first gate structure, first gate spacers formed on the sidewalls of the first gate structure, and first source and drain features and a second device di…
Who is the assignee on this patent?
Liu Chia-Chu, Chen Kuei Shun, Chiang Mu-Chi, and 6 more
What technology area does this patent fall under?
Primary CPC classification H10W20/0698. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).