Semiconductor device and method for preparing semiconductor device
US-2024339405-A1 · Oct 10, 2024 · US
Contact structure of semiconductor device priority claim
US8969201B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969201-B2 |
| Application number | US-201414469394-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 26, 2014 |
| Priority date | Nov 8, 2012 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a semiconductor device, comprising: providing a substrate comprising a major surface and a trench extending below the major surface; epitaxially growing a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; forming an inter-layer dielectric (ILD) layer over the strained material; forming an opening in the ILD layer to expose a portion of the…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969201B2 cover?
- The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer di…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10D64/0113. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).