Information processing apparatus and information processing method

Patent metadata

Field	Value
Publication number	US-8966166-B2
Application number	US-201213468370-A
Country	US
Kind code	B2
Filing date	May 10, 2012
Priority date	Jun 9, 2011
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

There is provided with an information processing apparatus comprising a DRAM, a memory controller configured to access the DRAM, and a bus master configured to send, to the memory controller, an access request to the DRAM, the bus master comprises a transmission unit configured to transmit, to the memory controller, using a signal indicating a type of burst access which is requested of the memory controller by the bus master, an instruction to designate that an auto-precharge operation is not to be performed after accessing the first address, and an instruction to designate that an auto-precharge operation is to be performed after accessing the first address.

First claim

What is claimed is:

1. A memory controlling system comprising:
a plurality of information processing apparatuses connected to a memory controller;
a memory; and
the memory controller, which accesses the memory,
wherein at least one of the plurality of information processing apparatuses comprises:
a specifying unit configured to specify a first address and a second address on the memory to be sequentially accessed by the information processing apparatus via the memory cont…

Assignees

• Nishioka Yoshio
• Takamura Akihiro
• Canon Kk

Inventors

• Nishioka Yoshio
• Takamura Akihiro

Classifications

• G06F13/16 Primary

  Physics · mapped topic

• G06F13/161

  Physics · mapped topic