Apparatus with data-rate-based voltage control mechanism and methods for operating the same
US-2024221813-A1 · Jul 4, 2024 · US
US8964498B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8964498-B2 |
| Application number | US-201213676864-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 14, 2012 |
| Priority date | Nov 15, 2011 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.
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What is claimed is: 1. A method for reducing an amount of peak power consumption in a semiconductor memory device, comprising: receiving a first signal and a second signal, wherein each of the first signal and the second signal is indicative of an amount of power consumed when data is transferred over a respective memory channel in the semiconductor memory device; combining the first signal with the second signal to generate a first combined signal; and shifting, in response t…
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