Semiconductor device having hierarchical bit line structure

Patent metadata

Field	Value
Publication number	US-8964439-B2
Application number	US-201313767481-A
Country	US
Kind code	B2
Filing date	Feb 14, 2013
Priority date	Feb 20, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A semiconductor device comprises first and second global bit lines, a sense amplifier amplifying a voltage difference of the first and second global bit lines, first and second local bit lines corresponding to the first and second global bit lines, and first and second hierarchical switches controlling electrical connections between the first and second global bit lines and the first and second local bit line. In a precharge operation prior to accessing a selected memory cell belong to the first local bit lines, a pair of the first and second hierarchical switches, which is not in an access path, is kept ON, and remaining ones thereof are kept OFF. Subsequently, in an access to the selected memory cell, a first hierarchical switch of the pair is switched from ON to OFF, and simultaneously a first hierarchical switches in the access path is switched from OFF to ON.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first global bit line;
a second global bit line;
a sense amplifier amplifying a voltage difference between the first and second global bit lines;
a plurality of first local bit lines arranged corresponding to the first global bit line;
a plurality of second local bit lines arranged corresponding to the second global bit line;
a plurality of first hierarchical switches controlling electrical connections bet…

Assignees

• Elpida Memory Inc
• Ps4 Luxco Sarl

Inventors

• Nagata Kyoichi

Classifications

• G11C11/4091 Primary

  Physics · mapped topic

• G11C7/12 Primary

  Physics · mapped topic

• G11C11/4097

  Physics · mapped topic

• G11C7/08

  Physics · mapped topic