PLL with oscillator PVT compensation

Patent metadata

Field	Value
Publication number	US-8963649-B2
Application number	US-201213731687-A
Country	US
Kind code	B2
Filing date	Dec 31, 2012
Priority date	Dec 31, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.

First claim

What is claimed is:

1. A voltage controlled oscillator (VCO), comprising:
a sensing circuit comprising a delay unit, the sensing circuit being configured to generate a plurality of compensation control signals in response to a time delay of the delay unit;
a voltage-to-current converter configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals; and
a current controlled oscillator configured to generate an oscillating signal in response to the current signal.

2. The VCO of claim 1 , wherein the sensing circuit comprises:
the delay unit configured to generate a pulse signal, the pulse signal having a pulse width representing the time delay of the delay unit; and
a signal converter configured to generate the plurality of compensation control signals in response to the pulse width of the pulse signal.

3. The VCO of claim 2 , wherein the delay unit comprises:
an AND gate having a first input terminal and a second input terminal, one of the first input terminal and the second input terminal being an inverted input terminal;
an input node electrically connected to the first input terminal of the AND gate; and
a plurality of buffers connected in series between the input node and the second input terminal of the AND gate.

4. The VCO of claim 2 , wherein the delay unit comprises:
a NAND gate having a first input terminal and a second input terminal;
an input node electrically connected to the first input terminal of the NAND gate; and
one or more inverters connected in series between the input node and the second input terminal of the NAND gate.

5. The VCO of claim 2 , wherein the signal converter comprises a counter configured to generate a count value based upon the pulse width of the pulse signal and output the count value, in a form of a binary code or a thermometer code, as the plurality of compensation control signals.

6. The VCO of claim 2 , wherein the signal converter comprises:
a charging circuit configured to generate a charged signal based upon the pulse width of the pulse signal; and
an analog-to-digital converter (ADC) configured to generate a digitized value of the charged signal and output the digitized value, in a form of a binary code or a thermometer code, as the plurality of compensation control signals.

7. The VCO of claim 2 , wherein the signal converter comprises:
a signal line configured to carry one of the plurality of compensation control signals; and
a low pass filter coupled to the signal line.

8. The VCO of claim 1 , wherein the voltage-to-current converter comprises:
an input node configured to receive the VCO control signal;
an output node configured to output the current signal;
a plurality of current sources configured to collectively generate the current signal at the output node; and
a plurality of switching circuits, each of the plurality of switching circuits being configured to selectively enable or disable a corresponding one of the plurality of current sources in response to a corresponding one of the plurality of compensation control signals.

9. The VCO of claim 8 , wherein
one of the plurality of current sources comprises a first transistor having a drain terminal coupled to the output node, a source terminal coupled to a power supply node, and a gate terminal; and
one of the plurality of switching circuits corresponding to the one of the plurality of current sources comprises:
a second transistor having a drain terminal coupled to the gate terminal of the first transistor and a source terminal coupled to the power supply node; and
a pass gate coupled between the gate terminal of the first transistor and the input node.

10. The VCO of claim 9 , wherein the one of the plurality of switching circuits corresponding to the one of the plurality of current sources comprises a low pass filter coupled to the gate terminal of the first transistor.

11. The VCO of claim 9 , wherein the pass gate comprises only a PMOS transistor, only an NMOS transistor, or both the PMOS transistor and the NMOS transistor connected as a transmission gate.

12. A Phase Lock Loop (PLL), comprising:
a phase detector configured to generate a phase detection signal based on a reference signal and a feedback signal;
a control signal generator configured to generate a voltage control signal in response to the phase detection signal;
a voltage controlled oscillator (VCO) configured to generate an output oscillating signal in response to the voltage control signal, the VCO comprising:
a sensing circuit comprising a delay unit, the sensing circuit configured to generate a plurality of compensation control signals in response to a time delay of the delay unit;
a voltage-to-current converter configured to generate a current signal in response to the voltage control signal and the plurality of compensation control signals; and
a current controlled oscillator configured to generate the output oscillating signal in response to the current signal; and

a divider configured to generate the feedback signal by frequency-dividing the output oscillating signal,
the sensing circuit and the current controlled oscillator being arranged without electrically forming a feedback loop.

13. The PLL of claim 12 , wherein the VCO has a VCO gain, the VCO gain has a VCO gain variation within a predetermined range of process or temperature variation of the VCO, and the delay unit, the voltage-to-current converter, and the sensing circuit are set to keep the VCO gain variation no greater than 15%.

14. The PLL of claim 12 , wherein
the sensing circuit comprises:
the delay unit configured to generate a pulse signal; and
a signal converter configured to generate the plurality of compensation control signals in response to the pulse width of the pulse signal; and

the voltage-to-current converter comprises:
a plurality of current sources configured to collectively generate the current signal; and
a plurality of switching circuits, each of the plurality of switching circuits being configured to enable and disable a corresponding one of the plurality of current sources in response to a corresponding one of the plurality of compensation control signals.

15. The PLL of claim 14 , wherein the delay unit comprises:
an AND gate having a first input terminal and a second input terminal, one of the first input terminal and the second input terminal being an inverted input terminal;
an input node electrically connected to the first input terminal of the AND gate; and
a plurality of buffers connected in series between the input node and the second input terminal of the AND gate.

16. The PLL of claim 14 , wherein the signal converter comprises a counter configured to generate a count value based upon the pulse width of the pulse signal and output the count value, in a form of a binary code or a thermometer code, as the plurality of compensation control signals.

17. The PLL of claim 14 , wherein the signal converter comprises:
a signal line configured to carry one of the plurality of compensation control signals; and
a capacitor coupled to the signal line.

18. A method of operating a voltage controlled oscillator (VCO), comprising:
generating a pulse signal according to a reference signal and a delayed reference signal;
converting a pulse width of the pulse signal to a plurality of compensation control signals, the plurality of compensation control signals corresponding to a value of the pulse width in a form of a binary code or a thermometer code;
selectively disablin

Assignees

• Li Matt
• Yuan Min-Shueh
• Chang Chih-Hsien
• Taiwan Semiconductor Mfg

Inventors

• Li Matt
• Yuan Min-Shueh
• Chang Chih-Hsien

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L1/00 Primary

  Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/06 Primary

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03B5/10

  active element in amplifier being vacuum tube (H03B5/14 takes precedence) · CPC title