Method for manufacturing a film on a support having a non-flat surface
US-12087615-B2 · Sep 10, 2024 · US
Method of fabricating isolated capacitors and structure thereof
US8963283B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8963283-B2 |
| Application number | US-201414230039-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 31, 2014 |
| Priority date | Jul 19, 2010 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.
First claim
Opening claim text (preview).
What is claimed: 1. A structure, comprising: one or more groups of deep trench capacitors formed in an SOI and n+ doped poly layer, and comprising an insulator material between and in direct contact with the n+ doped poly layer and a conductive plate formed in a trench; and one or more deep trench isolation structures formed in the SOI and n+ doped poly layer, which isolate at least one of the one or more groups of deep trench capacitors from another group.…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P90/1906Primary
Electricity · mapped topic
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- What does patent US8963283B2 cover?
- A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more iso…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10P90/1906. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).