Selective amorphization for electrical signal isolation and linearity in SOI structures

Patent metadata

Field	Value
Publication number	US-8963247-B2
Application number	US-201213670995-A
Country	US
Kind code	B2
Filing date	Nov 7, 2012
Priority date	Jan 13, 2012
Publication date	Feb 24, 2015
Grant date	Feb 24, 2015

Abstract

Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

First claim

The invention claimed is:

1. A structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of said structure, said structure comprising:
a gate situated on said top semiconductor layer, said top semiconductor layer situated over a base oxide layer, and said base oxide layer situated over a handle wafer;
wherein a top surface of said handle wafer is amorphized to form an amorphized region substantially aligned with said gate,…

Assignees

• Newport Fab Llc

Inventors

• Hurwitz Paul D
• Zwingman Robert L

Classifications

• H10W10/181

  Electricity · mapped topic

• H10P95/90

  Electricity · mapped topic

• H10P90/1906 Primary

  Electricity · mapped topic

• H10P90/192

  Electricity · mapped topic

• H10D86/201

  Electricity · mapped topic