Electronic device based on multilayer thin film and method for manufacturing the same using a three-dimensional structure
US-2024309503-A1 · Sep 19, 2024 · US
Method for fabricating capacitor with high aspect ratio
US8962437B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8962437-B2 |
| Application number | US-201213494400-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 12, 2012 |
| Priority date | Mar 19, 2012 |
| Publication date | Feb 24, 2015 |
| Grant date | Feb 24, 2015 |
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Abstract
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A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a capacitor, comprising: forming an etch stop layer over a semiconductor substrate having a storage node contact plug formed therein; forming a first silicon layer over the etch stop layer, wherein the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a silicon oxide layer…
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Electricity · mapped topic
Electricity · mapped topic
- H10D1/042Primary
Electricity · mapped topic
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- What does patent US8962437B2 cover?
- A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and …
- Who is the assignee on this patent?
- Kim Beom-Yong, Lee Kee-Jeung, Ji Yun-Hyuck, and 7 more
- What technology area does this patent fall under?
- Primary CPC classification H10D1/042. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).